1. Field of the Invention
The embodiments relate to integrated circuit design methods and, more particularly, to an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage.
2. Description of the Related Art
Integrated circuit design methods often incorporate both design-for-manufacturability (DFM) techniques and design-for-testability (DFT) techniques. DFM techniques typically involve making modifications to the layout of an integrated circuit based on a pre-established set of rules to improve the manufacturability of the integrated circuit (i.e., to improve yield and/or reliability of the integrated circuit, as manufactured). For example, DFM modifications can be made to enhance elements of individual cells, to enhance higher-level routing (e.g., by increasing wire widths and/or by providing redundant vias), to enhance memory redundancy, to increase spacing between wires or vias, to avoid particularly difficult to print layout patterns, etc. DFT techniques typically involve making modifications to the layout of an integrated circuit to improve testability (i.e., to improve test coverage during testing to validate the functioning the integrated circuit, as manufactured). For example, DFT modifications can include the addition of testable features to the layout of the integrated circuit in order to increase test coverage. It should be noted, however, that even with DFT modifications, 100% test coverage (e.g., test coverage of all nodes in an integrated circuit) is typically cost prohibitive, limited by design, test feasibility, and test time constraints. Furthermore, while both DFM and DFT techniques are incorporated into the design process, DFM modifications are typically made without consideration or knowledge of test coverage and vice versa.